The present invention relates generally to frequency synthesizers, and more particularly to an improved dual-bandwidth loop filter for use in frequency synthesizers of the type containing digital phase comparators.
In radio frequency synthesizers, it is desirable to have fast frequency locking characteristics when switching to a desired radio signal frequency, while at the same time, adequately attenuating reference signal feedthru and modulating the synthesizer output with signals having frequencies as low as 200 Hz once the synthesizer has locked onto the desired radio signal frequency. In order to provide fast frequency locking characteristics, prior art synthesizers, such as the described in U.S. Pat. No. 4,330,758, provide a wide loop bandwidth in order to lock quickly to a desired radio signal frequency and a narrower loop bandwidth once frequency lock has been obtained in order to attenuate reference signal feedthru. However, in switching from a wide to a narrow loop bandwidth, such prior art synthesizers typically introduce voltage transients which result in undesirable noise on the synthesizer output signal, the duration of which is stretched and emphasized due to the narrower loop bandwidth. Furthermore, much more costly and complex circuitry is required in the sample-and-hold phase comparator used in the synthesizer in U.S. Pat. No. 4,330,758 than in a digital phase comparator. In prior art synthesizers containing digital phase comparators, an extended modulation signal bandwidth has been obtained by modulating both the reference oscillator and the voltage-controlled oscillator. However, this scheme not only requires an expensive reference oscillator, but also results in excessive reference signal feedthru.